Regviz

stm32 /stm32f7 /STM32F730 /FMC /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IRS)IRS 0 (ILS)ILS 0 (IFS)IFS 0 (IREN)IREN 0 (ILEN)ILEN 0 (IFEN)IFEN 0 (FEMPT)FEMPT

Description

FIFO status and interrupt register

Fields

IRS

IRS
ILS

ILS
IFS

IFS
IREN

IREN
ILEN

ILEN
IFEN

IFEN
FEMPT

FEMPT

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32