Regviz

stm32 /stm32f7 /STM32F746 /FLASH /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOP)EOP 0 (OPERR)OPERR 0 (WRPERR)WRPERR 0 (PGAERR)PGAERR 0 (PGPERR)PGPERR 0 (PGSERR)PGSERR 0 (BSY)BSY

Description

Status register

Fields

EOP

End of operation
OPERR

Operation error
WRPERR

Write protection error
PGAERR

Programming alignment error
PGPERR

Programming parallelism error
PGSERR

Programming sequence error
BSY

Busy

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32