stm32 /stm32g0 /STM32G030 /RCC /BDCR

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Interpret as BDCR

31282724232019161512118743000000000000000000000000000000000000000000 (LSEON)LSEON0 (LSERDY)LSERDY0 (LSEBYP)LSEBYP0LSEDRV0 (LSECSSON)LSECSSON0 (LSECSSD)LSECSSD0RTCSEL0 (RTCEN)RTCEN0 (BDRST)BDRST0 (LSCOEN)LSCOEN0 (LSCOSEL)LSCOSEL

Description

RTC domain control register

Fields

LSEON

LSE oscillator enable

LSERDY

LSE oscillator ready

LSEBYP

LSE oscillator bypass

LSEDRV

LSE oscillator drive capability

LSECSSON

CSS on LSE enable

LSECSSD

CSS on LSE failure Detection

RTCSEL

RTC clock source selection

RTCEN

RTC clock enable

BDRST

RTC domain software reset

LSCOEN

Low-speed clock output (LSCO) enable

LSCOSEL

Low-speed clock output selection

Links

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