Regviz

stm32 /stm32g0 /STM32G030 /RCC /BDCR

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Interpret as BDCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0LSEDRV 0 (LSECSSON)LSECSSON 0 (LSECSSD)LSECSSD 0RTCSEL 0 (RTCEN)RTCEN 0 (BDRST)BDRST 0 (LSCOEN)LSCOEN 0 (LSCOSEL)LSCOSEL

Description

RTC domain control register

Fields

LSEON

LSE oscillator enable
LSERDY

LSE oscillator ready
LSEBYP

LSE oscillator bypass
LSEDRV

LSE oscillator drive capability
LSECSSON

CSS on LSE enable
LSECSSD

CSS on LSE failure Detection
RTCSEL

RTC clock source selection
RTCEN

RTC clock enable
BDRST

RTC domain software reset
LSCOEN

Low-speed clock output (LSCO) enable
LSCOSEL

Low-speed clock output selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32