Regviz

stm32 /stm32g0 /STM32G030 /SPI1 /I2SCFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as I2SCFGR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32g0/STM32G030/SPI1/I2SCFGR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHLEN)CHLEN 0DATLEN 0 (CKPOL)CKPOL 0I2SSTD 0 (PCMSYNC)PCMSYNC 0I2SCFG 0 (SE2)SE2 0 (I2SMOD)I2SMOD

Description

configuration register

Fields

CHLEN

Channel length (number of bits per audio channel)
DATLEN

Data length to be transferred
CKPOL

Inactive state clock polarity
I2SSTD

standard selection
PCMSYNC

PCM frame synchronization
I2SCFG

I2S configuration mode
SE2

I2S enable
I2SMOD

I2S mode selection

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32