stm32 /stm32g0 /STM32G051 /HDMI_CEC /CEC_CFGR

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Interpret as CEC_CFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SFT0 (B_0x0)RXTOL 0 (B_0x0)BRESTP 0 (B_0x0)BREGEN 0 (B_0x0)LBPEGEN 0 (B_0x0)BRDNOGEN 0 (B_0x0)SFTOP 0OAR0 (B_0x0)LSTN

BRESTP=B_0x0, LSTN=B_0x0, LBPEGEN=B_0x0, RXTOL=B_0x0, BRDNOGEN=B_0x0, BREGEN=B_0x0, SFTOP=B_0x0

Description

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.

Fields

SFT

Signal free time

1 (B_0x1): 0.5 nominal data bit periods

2 (B_0x2): 1.5 nominal data bit periods

3 (B_0x3): 2.5 nominal data bit periods

4 (B_0x4): 3.5 nominal data bit periods

5 (B_0x5): 4.5 nominal data bit periods

6 (B_0x6): 5.5 nominal data bit periods

7 (B_0x7): 6.5 nominal data bit periods

RXTOL

Rx-tolerance

0 (B_0x0): Standard tolerance margin:

1 (B_0x1): Extended tolerance

BRESTP

Rx-stop on bit rising error The BRESTP bit is set and cleared by software.

0 (B_0x0): BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.

1 (B_0x1): BRE detection stops message reception.

BREGEN

Generate error-bit on bit rising error

0 (B_0x0): BRE detection does not generate an error-bit on the CEC line.

1 (B_0x1): BRE detection generates an error-bit on the CEC line (if BRESTP is set).

LBPEGEN

Generate error-bit on long bit period error

0 (B_0x0): LBPE detection does not generate an error-bit on the CEC line.

1 (B_0x1): LBPE detection generates an error-bit on the CEC line.

BRDNOGEN

Avoid error-bit generation in broadcast

0 (B_0x0): BRE detection with BRESTP = 1 and BREGEN = 0 on a broadcast message generates an

1 (B_0x1): Error-bit is not generated in the same condition as above. An error-bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set.

SFTOP

SFT option bit The SFTOPT bit is set and cleared by software.

0 (B_0x0): SFT timer starts when TXSOM is set by software.

1 (B_0x1): SFT timer starts automatically at the end of message transmission/reception.

OAR

Own addresses configuration

LSTN

Listen mode LSTN bit is set and cleared by software.

0 (B_0x0): CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

1 (B_0x1): CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

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