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stm32 /stm32g0 /STM32G070 /UCPD1 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TXMODE 0 (TXSEND)TXSEND 0 (TXHRST)TXHRST 0 (RXMODE)RXMODE 0 (PHYRXEN)PHYRXEN 0 (PHYCCSEL)PHYCCSEL 0ANASUBMODE 0 (ANAMODE)ANAMODE 0CCENABLE 0 (DBATTEN)DBATTEN 0 (FRSRXEN)FRSRXEN 0 (FRSTX)FRSTX 0 (RDCH)RDCH 0 (CC1TCDIS)CC1TCDIS 0 (CC2TCDIS)CC2TCDIS

Description

UCPD control register

Fields

TXMODE

TXMODE
TXSEND

TXSEND
TXHRST

TXHRST
RXMODE

RXMODE
PHYRXEN

PHYRXEN
PHYCCSEL

PHYCCSEL
ANASUBMODE

ANASUBMODE
ANAMODE

ANAMODE
CCENABLE

CCENABLE
DBATTEN

DBATTEN
FRSRXEN

FRSRXEN
FRSTX

FRSTX
RDCH

RDCH
CC1TCDIS

CC1TCDIS
CC2TCDIS

CC2TCDIS

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32