CCF=B_0x0, RDERR=B_0x0, WRERR=B_0x0, BUSY=B_0x0
AES status register
| CCF | Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. 0 (B_0x0): Not completed 1 (B_0x1): Completed |
| RDERR | Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero. 0 (B_0x0): Not detected 1 (B_0x1): Detected |
| WRERR | Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored. 0 (B_0x0): Not detected 1 (B_0x1): Detected |
| BUSY | Busy 0 (B_0x0): Idle 1 (B_0x1): Busy |