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stm32 /stm32g4 /STM32G431 /FDCAN /FDCAN_TSCC

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Interpret as FDCAN_TSCC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TSS0TCP

TSS=B_0x0

Description

FDCAN timestamp counter configuration register

Fields

TSS

Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

0 (B_0x0): Timestamp counter value always 0x0000

1 (B_0x1): Timestamp counter value incremented according to TCP

2 (B_0x2): External timestamp counter from TIM3 value (tim3_cnt[0:15])

3 (B_0x3): Same as 00.
TCP

Timestamp counter prescaler

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32