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stm32 /stm32g4 /STM32G431 /SYSCFG /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLL)CLL 0 (SPL)SPL 0 (PVDL)PVDL 0 (ECCL)ECCL 0 (SPF)SPF

Description

configuration register 2

Fields

CLL

Core Lockup Lock
SPL

SRAM Parity Lock
PVDL

PVD Lock
ECCL

ECC Lock
SPF

SRAM Parity Flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32