POLARITY=B_0x0, SCALEN=B_0x0, BRGEN=B_0x0, ITEN=B_0x0, EN=B_0x0, HYST=B_0x0, LOCK=B_0x0, PWRMODE=B_0x0, BLANKING=B_0x0
Comparator configuration register 1
| EN | COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP Channel1. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| BRGEN | Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V REF_COMP (similar to V REFINT ). If SCALEN and BRGEN are set, the four scaler outputs provide V REF_COMP , 3/4 V REF_COMP , 1/2 V REF_COMP and 1/4 V REF_COMP levels, respectively. 0 (B_0x0): Scaler resistor bridge disabled 1 (B_0x1): Scaler resistor bridge enabled |
| SCALEN | Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the V REFINT scaler for the COMP channels. 0 (B_0x0): V REFINT scaler disabled 1 (B_0x1): V REFINT scaler enabled |
| POLARITY | COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity. 0 (B_0x0): COMP channel1 output is not inverted 1 (B_0x1): COMP Channel1 output is inverted |
| ITEN | COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1. 0 (B_0x0): Interrupt generation disabled for COMP channel1 1 (B_0x1): Interrupt generation enabled for COMP channel1 |
| HYST | COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1. 0 (B_0x0): No hysteresis 1 (B_0x1): Low hysteresis 2 (B_0x2): Medium hysteresis 3 (B_0x3): High hysteresis |
| PWRMODE | Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1. 0 (B_0x0): High speed/high power 1 (B_0x1): Medium speed/medium power 2 (B_0x2): Medium speed/medium power 3 (B_0x3): Ultra low power/ultra-low-power |
| INMSEL | COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table 146: COMP1 inverting input assignment for more details. |
| INPSEL1 | COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table 145: COMP1 noninverting input assignment for more details. |
| INPSEL2 | COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table 145: COMP1 noninverting input assignment for more details. |
| BLANKING | COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved 0 (B_0x0): No blanking 1 (B_0x1): comp_blk1 2 (B_0x2): comp_blk2 3 (B_0x3): comp_blk3 4 (B_0x4): comp_blk4 5 (B_0x5): comp_blk5 6 (B_0x6): comp_blk6 |
| LOCK | Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0] 0 (B_0x0): COMP_CFGR1[31:0] register is read/write 1 (B_0x1): COMP_CFGR1[31:0] is read-only |