LOCK=B_0x0
Comparator configuration register 2
| INPSEL0 | COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table 145: COMP1 noninverting input assignment for more details. |
| LOCK | Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0] 0 (B_0x0): COMP_CFGR2[31:0] register is read/write 1 (B_0x1): COMP_CFGR2[31:0] is read-only |