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stm32 /stm32h5 /STM32H503 /COMP /COMP_SR

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Interpret as COMP_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (C1VAL)C1VAL 0 (C1IF)C1IF

Description

Comparator status register

Fields

C1VAL

COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
C1IF

COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32