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stm32 /stm32h5 /STM32H503 /DAC /DAC_DHR8R1

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Interpret as DAC_DHR8R1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DACC1DHR0DACC1DHRB

Description

DAC channel1 8-bit right aligned data holding register

Fields

DACC1DHR

DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1.
DACC1DHRB

DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1 when the DAC operates in Double data mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32