Regviz

stm32 /stm32h5 /STM32H503 /DAC /DAC_DHR8R2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DAC_DHR8R2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H503/DAC/DAC_DHR8R2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DACC2DHR0DACC2DHRB

Description

DAC channel2 8-bit right-aligned data holding register

Fields

DACC2DHR

DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
DACC2DHRB

DAC channel2 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel2 when the DAC operates in Double data mode.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32