MODE1=B_0x0, SINFORMAT1=B_0x0, DMADOUBLE1=B_0x0, HFSEL0=B_0x0, MODE2=B_0x0, HFSEL1=B_0x0, DMADOUBLE2=B_0x0, SINFORMAT2=B_0x0
DAC mode control register
| MODE1 | DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN1 = 0. 0 (B_0x0): DAC channel1 is connected to external pin with Buffer enabled 1 (B_0x1): DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled 2 (B_0x2): DAC channel1 is connected to external pin with Buffer disabled 3 (B_0x3): DAC channel1 is connected to on chip peripherals with Buffer disabled 4 (B_0x4): DAC channel1 is connected to external pin with Buffer enabled 5 (B_0x5): DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled 6 (B_0x6): DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled 7 (B_0x7): DAC channel1 is connected to on chip peripherals with Buffer disabled |
| DMADOUBLE1 | DAC channel1 DMA double data mode This bit is set and cleared by software. 0 (B_0x0): DMA Normal mode selected 1 (B_0x1): DMA Double data mode selected |
| SINFORMAT1 | Enable signed format for DAC channel1 This bit is set and cleared by software. 0 (B_0x0): Input data is in unsigned format 1 (B_0x1): Input data is in signed format (2’s complement). The MSB bit represents the sign. |
| HFSEL0 | High frequency interface mode selection 0 (B_0x0): High frequency interface mode disabled 1 (B_0x1): High frequency interface mode compatible to AHB80 MHz enabled |
| HFSEL1 | High frequency interface mode selection 0 (B_0x0): High frequency interface mode disabled 1 (B_0x1): High frequency interface mode compatible to AHB80 MHz enabled |
| MODE2 | DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2 = 0 and bit CEN2 = 0 in the DAC_CR register). If EN2 = 1 or CEN2 = 1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2 = 0. Refer to for the availability of DAC channel2. 0 (B_0x0): DAC channel2 is connected to external pin with Buffer enabled 2 (B_0x2): DAC channel2 is connected to external pin with buffer disabled 4 (B_0x4): DAC channel2 is connected to external pin with Buffer enabled 6 (B_0x6): DAC channel2 is connected to external pin with Buffer disabled |
| DMADOUBLE2 | DAC channel2 DMA double data mode This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): DMA Normal mode selected 1 (B_0x1): DMA Double data mode selected |
| SINFORMAT2 | Enable signed format for DAC channel2 This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): Input data is in unsigned format 1 (B_0x1): Input data is in signed format (2’s complement). The MSB bit represents the sign. |