DAC sample and hold time register
| THOLD1 | DAC channel1 hold time (only valid in Sample and hold mode) Hold time = (THOLD[9:0]) x LSI/LSE clock period Note: This register can be modified only when EN1 = 0. |
| THOLD2 | DAC channel2 hold time (only valid in Sample and hold mode). Hold time = (THOLD[9:0]) x LSI/LSE clock period Note: This register can be modified only when EN2 = 0. These bits are available only on dual-channel DACs. Refer to implementation. |