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stm32 /stm32h5 /STM32H503 /DBGMCU /DBGMCU_APB1HFZR

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Interpret as DBGMCU_APB1HFZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_LPTIM2_STOP

DBG_LPTIM2_STOP=B_0x0

Description

DBGMCU APB1H peripheral freeze register

Fields

DBG_LPTIM2_STOP

LPTIM2 stop in debug

0 (B_0x0): normal operation. LPTIM2 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. LPTIM2 is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32