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stm32 /stm32h5 /STM32H503 /DBGMCU /DBGMCU_APB3FZR

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Interpret as DBGMCU_APB3FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_I3C2_STOP 0 (B_0x0)DBG_LPTIM1_STOP 0 (B_0x0)DBG_RTC_STOP

DBG_RTC_STOP=B_0x0, DBG_I3C2_STOP=B_0x0, DBG_LPTIM1_STOP=B_0x0

Description

DBGMCU APB3 peripheral freeze register

Fields

DBG_I3C2_STOP

I3C2 SCL stall counter stop in debug

0 (B_0x0): normal operation. I3C2 SCL stall timeout counter continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. I3C2 SCL stall timeout counter is frozen while CPU is in debug mode.
DBG_LPTIM1_STOP

LPTIM1 stop in debug

0 (B_0x0): normal operation. LPTIM1 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. LPTIM1 is frozen while CPU is in debug mode.
DBG_RTC_STOP

RTC stop in debug

0 (B_0x0): normal operation. RTC continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. RTC is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32