RegViz: Visualize EXTI

stm32 /stm32h5 /STM32H503 /EXTI /EXTI_EMR1

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Interpret as EXTI_EMR1

EM17=B_0x0, EM9=B_0x0, EM24=B_0x0, EM8=B_0x0, EM28=B_0x0, EM11=B_0x0, EM26=B_0x0, EM14=B_0x0, EM12=B_0x0, EM6=B_0x0, EM15=B_0x0, EM7=B_0x0, EM5=B_0x0, EM4=B_0x0, EM1=B_0x0, EM27=B_0x0, EM13=B_0x0, EM19=B_0x0, EM16=B_0x0, EM10=B_0x0, EM2=B_0x0, EM0=B_0x0, EM22=B_0x0, EM3=B_0x0, EM29=B_0x0, EM21=B_0x0, EM25=B_0x0

Description

EXTI CPU wakeup with event mask register

Fields

EM0	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM1	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM2	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM3	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM4	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM5	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM6	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM7	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM8	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM9	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM10	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM11	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM12	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM13	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM14	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM15	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM16	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM17	CPU wakeup with event generation mask on event input x (x = 17 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM19	CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM21	CPU wakeup with event generation mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM22	CPU wakeup with event generation mask on event input x (x = 22 to 21) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM24	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM25	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM26	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM27	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM28	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM29	CPU wakeup with event generation mask on event input x (x = 29 to 24) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.

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