RegViz: Visualize EXTI

stm32 /stm32h5 /STM32H503 /EXTI /EXTI_EMR2

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Interpret as EXTI_EMR2

EM42=B_0x0, EM50=B_0x0, EM40=B_0x0, EM37=B_0x0, EM39=B_0x0, EM38=B_0x0, EM41=B_0x0, EM53=B_0x0, EM49=B_0x0, EM47=B_0x0

Description

EXTI CPU wakeup with event mask register 2

Fields

EM37	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM38	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM39	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM40	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM41	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM42	CPU wakeup with event generation mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM47	CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM49	CPU wakeup with event generation mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM50	CPU wakeup with event generation mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.
EM53	CPU wakeup with event generation mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with event generation from Line x is masked. 1 (B_0x1): Wakeup with event generation from Line x is unmasked.

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