EXTI0=B_0x0, EXTI1=B_0x0, EXTI3=B_0x0, EXTI2=B_0x0
EXTI external interrupt selection register
EXTI0 | EXTI0 GPIO port selection These bits are written by software to select the source input for EXTI0 external interrupt. When EXTI_PRIVCFGR.PRIV0 is disabled, EXTI0 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV0 is enabled, EXTI0 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 (B_0x0): PA[0] pin 1 (B_0x1): PB[0] pin 2 (B_0x2): PC[0] pin 7 (B_0x7): PH[0] pin |
EXTI1 | EXTI1 GPIO port selection These bits are written by software to select the source input for EXTI1 external interrupt. When EXTI_PRIVCFGR.PRIV1 is disabled, EXTI1 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV1 is enabled, EXTI1 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 (B_0x0): PA[1] pin 1 (B_0x1): PB[1] pin 2 (B_0x2): PC[1] pin 7 (B_0x7): PH[1] pin |
EXTI2 | EXTI2 GPIO port selection These bits are written by software to select the source input for EXTI2 external interrupt. When EXTI_PRIVCFGR.PRIV2 is disabled, EXTI2 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV2 is enabled, EXTI2 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 (B_0x0): PA[2] pin 1 (B_0x1): PB[2] pin 2 (B_0x2): PC[2] pin 3 (B_0x3): PD[2] pin |
EXTI3 | EXTI3 GPIO port selectio These bits are written by software to select the source input for EXTI3 external interrupt. When EXTI_PRIVCFGR.PRIV3 is disabled, EXTI3 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV3 is enabled, EXTI3 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 (B_0x0): PA[3] pin 1 (B_0x1): PB[3] pin 2 (B_0x2): PC[3] pin |