RegViz: Visualize EXTI

stm32 /stm32h5 /STM32H503 /EXTI /EXTI_IMR2

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Interpret as EXTI_IMR2

IM47=B_0x0, IM53=B_0x0, IM49=B_0x0, IM50=B_0x0, IM42=B_0x0, IM37=B_0x0, IM41=B_0x0, IM40=B_0x0, IM39=B_0x0, IM38=B_0x0

Description

EXTI CPU wakeup with interrupt mask register 2

Fields

IM37	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM38	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM39	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM40	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM41	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM42	CPU wakeup with interrupt mask on event input x (x = 42 to 37) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM47	CPU wakeup with interrupt mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM49	CPU wakeup with interrupt mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM50	CPU wakeup with interrupt mask on event input x (x = 50 to 49) When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.
IM53	CPU wakeup with interrupt mask on event input x When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 (B_0x0): Wakeup with interrupt request from input event x is masked. 1 (B_0x1): Wakeup with interrupt request from input event x is unmasked.

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