SWI16=B_0x0, SWI9=B_0x0, SWI10=B_0x0, SWI7=B_0x0, SWI12=B_0x0, SWI13=B_0x0, SWI6=B_0x0, SWI0=B_0x0, SWI11=B_0x0, SWI3=B_0x0, SWI2=B_0x0, SWI15=B_0x0, SWI14=B_0x0, SWI8=B_0x0, SWI4=B_0x0, SWI5=B_0x0, SWI1=B_0x0
EXTI software interrupt event register
| SWI0 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI1 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI2 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI3 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI4 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI5 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI6 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI7 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI8 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI9 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI10 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI11 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI12 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI13 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI14 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI15 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |
| SWI16 | Software interrupt on event x (x = 16 to 0) When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 (B_0x0): Writing 0 has no effect. 1 (B_0x1): Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. |