PRFTEN=B_0x0, S_PRFTEN=B_0x0, LATENCY=B_0x0
FLASH access control register
| LATENCY | Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. … Note: No check is performed by hardware to verify that the configuration is correct. 0 (B_0x0): zero wait state used to read a word from non-volatile memory 1 (B_0x1): one wait state used to read a word from non-volatile memory 2 (B_0x2): two wait states used to read a word from non-volatile memory 7 (B_0x7): seven wait states used to read a word from non-volatile memory 15 (B_0xF): 15 wait states used to read from non-volatile memory |
| WRHIGHFREQ | Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies. |
| PRFTEN | Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. 0 (B_0x0): prefetch disabled. 1 (B_0x1): prefetch enabled when latency is at least one wait state. |
| S_PRFTEN | Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality. 0 (B_0x0): prefetch, if enabled fetches each instruction. 1 (B_0x1): prefetch, if enabled avoids fetch past branch to improve efficiency. |