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stm32 /stm32h5 /STM32H503 /FLASH /FLASH_OPSR

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Interpret as FLASH_OPSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDR_OP0 (BK_OP)BK_OP 0 (SYSF_OP)SYSF_OP 0 (OTP_OP)OTP_OP 0 (B_0x0)CODE_OP

CODE_OP=B_0x0

Description

FLASH operation status register

Fields

ADDR_OP

Interrupted operation address.
BK_OP

Interrupted operation bank It indicates which bank was concerned by operation.
SYSF_OP

Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash.
OTP_OP

OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area.
CODE_OP

Flash memory operation code

0 (B_0x0): No Flash operation on going during previous reset

1 (B_0x1): Single write operation interrupted

3 (B_0x3): Sector erase operation interrupted

4 (B_0x4): Bank erase operation interrupted

5 (B_0x5): Mass erase operation interrupted

6 (B_0x6): Option change operation interrupted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32