stm32 /stm32h5 /STM32H503 /FLASH /FLASH_OPTSR2_PRG

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Interpret as FLASH_OPTSR2_PRG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SRAM2_RST 0 (B_0x0)BKPRAM_ECC 0 (B_0x0)SRAM2_ECC 0 (B_0x0)SRAM1_RST 0 (B_0x0)SRAM1_ECC

SRAM2_ECC=B_0x0, SRAM1_RST=B_0x0, BKPRAM_ECC=B_0x0, SRAM2_RST=B_0x0, SRAM1_ECC=B_0x0

Description

FLASH option status register 2

Fields

SRAM2_RST

SRAM2 erase when system reset

0 (B_0x0): SRAM2 erased when a system reset occurs

1 (B_0x1): SRAM2 not erased when a system reset occurs.

BKPRAM_ECC

Backup RAM ECC detection and correction disable

0 (B_0x0): BKPRAM ECC check enabled

1 (B_0x1): BKPRAM ECC check disabled

SRAM2_ECC

SRAM2 ECC detection and correction disable

0 (B_0x0): SRAM2 ECC check enabled

1 (B_0x1): SRAM2 ECC check disabled

SRAM1_RST

SRAM1 erase upon system reset

0 (B_0x0): SRAM1 erased when a system reset occurs

1 (B_0x1): SRAM1 not erased when a system reset occurs

SRAM1_ECC

SRAM1 ECC detection and correction disable

0 (B_0x0): SRAM1 ECC check enabled

1 (B_0x1): SRAM1 ECC check disabled

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