IWDG_SW=B_0x0, BORH_EN=B_0x0, NRST_SHDW=B_0x0, WWDG_SW=B_0x0, IO_VDD_HSLV=B_0x0, BOR_LEV=B_0x0, IWDG_STDBY=B_0x0, IWDG_STOP=B_0x0, IO_VDDIO2_HSLV=B_0x0, NRST_STOP=B_0x0, SWAP_BANK=B_0x0, NRST_STDBY=B_0x0
FLASH option status register
| BOR_LEV | Brownout level option configuration bit These bits reflects the power level that generates a system reset. 0 (B_0x0): BOR OFF, POR/PDR reset threshold level is applied 1 (B_0x1): BOR Level 1, the threshold level is low (around 2.1 V) 2 (B_0x2): BOR Level 2, the threshold level is medium (around 2.4 V) 3 (B_0x3): BOR Level 3, the threshold level is high (around 2.7 V) |
| BORH_EN | Brownout high enable configuration bit 0 (B_0x0): disabled 1 (B_0x1): enabled |
| IWDG_SW | IWDG control mode option configuration bit 0 (B_0x0): IWDG watchdog is controlled by hardware 1 (B_0x1): IWDG watchdog is controlled by software |
| WWDG_SW | WWDG control mode option configuration bit 0 (B_0x0): WWDG watchdog is controlled by hardware 1 (B_0x1): WWDG watchdog is controlled by software |
| NRST_SHDW | Core domain Shutdown entry reset option configuration bit 0 (B_0x0): a reset is generated when entering Shutdown mode on core domain 1 (B_0x1): no reset generated when entering Shutdown mode on core domain. |
| NRST_STOP | Core domain Stop entry reset option configuration bit 0 (B_0x0): a reset is generated when entering Stop mode on core domain 1 (B_0x1): no reset generated when entering Stop mode on core domain. |
| NRST_STDBY | Core domain Standby entry reset option configuration bit 0 (B_0x0): a reset is generated when entering Standby mode on core domain 1 (B_0x1): no reset generated when entering Standby mode on core domain. |
| PRODUCT_STATE | Life state code (based on Hamming 8,4). More information in . |
| IO_VDD_HSLV | High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.5 V. 0 (B_0x0): High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) 1 (B_0x1): High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) |
| IO_VDDIO2_HSLV | High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.5 V. 0 (B_0x0): High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) 1 (B_0x1): High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) |
| IWDG_STOP | IWDG Stop mode freeze option configuration bit When set the independent watchdog IWDG is in system Stop mode. 0 (B_0x0): Independent watchdog frozen in system Stop mode 1 (B_0x1): Independent watchdog keep running in system Stop mode. |
| IWDG_STDBY | IWDG Standby mode freeze option configuration bit When set the independent watchdog IWDG is frozen in system Standby mode. 0 (B_0x0): Independent watchdog frozen in Standby mode 1 (B_0x1): Independent watchdog keep running in Standby mode. |
| SWAP_BANK | Bank swapping option configuration bit SWAP_BANK option bit is used to configure whether the Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register after a reset. 0 (B_0x0): Bank1 and Bank2 not swapped 1 (B_0x1): Bank1 and Bank2 swapped |