stm32 /stm32h5 /STM32H503 /GTZC1 /GTZC1_TZSC_MPCWM4BCFGR

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Interpret as GTZC1_TZSC_MPCWM4BCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SREN 0 (B_0x0)SRLOCK 0 (B_0x0)PRIV

SRLOCK=B_0x0, SREN=B_0x0, PRIV=B_0x0

Description

GTZC1 TZSC BKPSRAM sub-region B watermark configuration register

Fields

SREN

Sub-region z enable

0 (B_0x0): Sub-region z is disabled. Access control of base region applies to any access between this sub-region start- and end-addresses.

1 (B_0x1): Sub-region z is enabled. Access control defined in GTZC1_TZSC_MPCWMzCFGR applies to any access between this sub-region start- and end-addresses, both defined in GTZC1_TZSC_MPCWMAR and GTZC1_TZSC_MPCWMBR.

SRLOCK

Sub-region z lock This bit, once set, can be cleared only by a system reset.

0 (B_0x0): GTZC1_TZSC_MPCWMzCFGR, GTZC1_TZSC_MPCWMAR and GTZC1_TZSC_MPCWMBR can be written.

1 (B_0x1): Writes to GTZC1_TZSC_MPCWMzCFGR, GTZC1_TZSC_MPCWMAR and GTZC1_TZSC_MPCWMBR are ignored.

PRIV

Privileged sub-region z This bit is taken into account only if SREN is set.

0 (B_0x0): Privileged and unprivileged accesses are granted in sub-region z.

1 (B_0x1): Only privileged accesses are granted in sub-region z.

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