stm32 /stm32h5 /STM32H503 /I3C1 /I3C_CR

count of data to transfer during a read or write message, in bytes (whatever I3C is acting as controller/target) Linear encoding up to 64 Kbytes -1 …

0 (B_0x0): no data to transfer

1 (B_0x1): 1 byte

2 (B_0x2): 2 bytes

65535 (B_0xFFFF): 64 Kbytes - 1 byte

read / non-write message (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message), in order to emit the RnW bit on the I3C bus.

0 (B_0x0): write message

1 (B_0x1): read message

7-bit I3C dynamic / I2C static target address (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message)

message type (whatever I3C is acting as controller/target) Bits[26:0] are ignored. After M2 error detection on an I3C SDR message, this is needed for SCL ‘stuck at’ recovery. Bits[26:0] are ignored. If I3C_CFGR.EXITPTRN=1, an HDR exit pattern is emitted on the bus to generate an escalation fault. Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred private message is: {S / S+7’h7E+RnW=0+Sr / Sr+} + 7-bit DynAddr + RnW + (8-bit Data + T) + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred direct message is: Sr + 7-bit DynAddr + RnW + (8-bit Data + T) + Sr/P Bits[23:17] (ADD[6:0]) is the emitted 7-bit static address. Bit[16] (RNW) is the emitted RnW bit. The transferred legacy I2C message is: {S / S+ 7’h7E+RnW=0 + Sr / Sr+} + 7-bit StaAddr + RnW + (8-bit Data + T) + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). 1xxx: reserved (when I3C is acting as I3C controller, used when target) 0xxx: reserved {S +} 7’h02 addr + RnW=0 {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=0 after a bus available condition (the target first emits a START request), or once the controller drives a START. {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=1 (+Ack/Nack from controller) When acknowledged from controller, the next (optional, depending on I3C_BCR.BCR2) transmitted IBI payload data is defined by I3C_CR.DCNT[15:0] and must be consistently programmed vs the maximum IBI payload data size which is defined by I3C_IBIDR.IBIP[2:0]. Others: reserved

0 (B_0x0_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): SCL output clock stops running until next control word is executed

1 (B_0x1_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): header message

2 (B_0x2_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): private message

3 (B_0x3_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): direct message (2nd part of an I3C SDR direct CCC command)

4 (B_0x4_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): legacy I2C message

6 (B_0x6_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): reserved (for this 1st alternate register description)

8 (B_0x8_WHEN_I3C_IS_ACTING_AS_I3C_TARGET): hot-join request (W)

9 (B_0x9_WHEN_I3C_IS_ACTING_AS_I3C_TARGET): controller-role request (W)

10 (B_0xA_WHEN_I3C_IS_ACTING_AS_I3C_TARGET): IBI (in-band interrupt) request ®

message end type (when the I3C is acting as controller)

0 (B_0x0): this message from controller ends with a Repeated START (Sr)

1 (B_0x1): this message from controller ends with a STOP (P), being the last message of a frame