STALLA=B_0x0
I3C timing register 2
| STALLT | Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent. |
| STALLD | controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data. |
| STALLC | controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command. |
| STALLA | controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt. 0 (B_0x0): no stall 1 (B_0x1): stall enabled |
| STALL | controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK |