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stm32 /stm32h5 /STM32H503 /PWR /PWR_BDSR

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Interpret as PWR_BDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BRRDY 0 (B_0x0)VBATL 0 (B_0x0)VBATH 0 (B_0x0)TEMPL 0 (B_0x0)TEMPH

TEMPL=B_0x0, VBATL=B_0x0, TEMPH=B_0x0, BRRDY=B_0x0, VBATH=B_0x0

Description

PWR Backup domain status register

Fields

BRRDY

backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready.

0 (B_0x0): backup regulator not ready

1 (B_0x1): backup regulator ready
VBATL

V BAT level monitoring versus low threshold

0 (B_0x0): V BAT level above low threshold level

1 (B_0x1): V BAT level equal or below low threshold level
VBATH

V BAT level monitoring versus high threshold

0 (B_0x0): V BAT level below high threshold level

1 (B_0x1): V BAT level equal or above high threshold level
TEMPL

temperature level monitoring versus low threshold

0 (B_0x0): temperature above low threshold level

1 (B_0x1): temperature equal or below low threshold level
TEMPH

temperature level monitoring versus high threshold

0 (B_0x0): temperature below high threshold level

1 (B_0x1): temperature equal or above high threshold level

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32