stm32 /stm32h5 /STM32H503 /PWR /PWR_IORETR

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Interpret as PWR_IORETR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IORETEN 0 (B_0x0)JTAGIORETEN

IORETEN=B_0x0, JTAGIORETEN=B_0x0

Description

PWR I/O retention register

Fields

IORETEN

IO retention enable: When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register.

0 (B_0x0): IO Retention mode is disabled.

1 (B_0x1): IO Retention mode is enabled for all IOs except the ones supporting the standby functionality (PC13, PC14 and PC15) and JTAG I/Os (PA13, PA14, PA15, PB4).

JTAGIORETEN

IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode

0 (B_0x0): IO Retention mode is disabled.

1 (B_0x1): IO Retention mode is enabled for PA13, PA14, PA15 and PB4.

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