BOOSTE=B_0x0, CSSF=B_0x0, SRAM1SO=B_0x0, LPMS=B_0x0, FLPS=B_0x0, SRAM2SO=B_0x0, AVD_READY=B_0x0
PWR power mode control register
| LPMS | low-power mode selection This bit defines the Deepsleep mode. 0 (B_0x0): Keeps Stop mode when entering DeepSleep. 1 (B_0x1): Allows Standby mode when entering DeepSleep. |
| SVOS | system Stop mode voltage scaling selection These bits control the V CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. 1 (B_0x1): SVOS5 scale 5 2 (B_0x2): SVOS4 scale 4 3 (B_0x3): SVOS3 scale 3 (default). |
| CSSF | clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. 0 (B_0x0): no effect 1 (B_0x1): STOPF and SBF flags cleared. |
| FLPS | Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. 0 (B_0x0): Flash memory remains in normal mode when the CPU domain enters Stop mode (quick restart time). 1 (B_0x1): Flash memory enters low-power mode when the CPU domain enters Stop mode (low power consumption). |
| BOOSTE | analog switch V BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V DD supply voltage can be monitored through the PVD and the PLS bits. 0 (B_0x0): booster disabled (default) 1 (B_0x1): booster enabled if analog voltage ready (AVD_READY = 1). |
| AVD_READY | analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored (ALS bits). 0 (B_0x0): peripheral analog voltage V DDA not ready (default) 1 (B_0x1): peripheral analog voltage V DDA ready. |
| SRAM2SO | AHB SRAM2 shut-off in Stop mode. 0 (B_0x0): AHB RAM2 content is kept in Stop mode. 1 (B_0x1): AHB RAM2 content is lost in Stop mode. |
| SRAM1SO | AHB SRAM1 shut-off in Stop mode 0 (B_0x0): AHB RAM1 content is kept in Stop mode. 1 (B_0x1): AHB RAM1 content is lost in Stop mode. |