PVDO=B_0x0, AVDO=B_0x0, VDDIO2RDY=B_0x0
PWR voltage monitor status register
| AVDO | analog voltage detector output on V DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. 0 (B_0x0): V DDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. 1 (B_0x1): V DDA is lower than the AVD threshold selected with the ALS[2:0] bits. |
| VDDIO2RDY | voltage detector output on V DDIO2 This bit is set and cleared by hardware. 0 (B_0x0): V DDIO2 is below 1.2 V. 1 (B_0x1): V DDIO2 is above or equal to 1.2 V. |
| PVDO | programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. 0 (B_0x0): V DD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. 1 (B_0x1): V DD is lower than the PVD threshold selected through the PLS[2:0] bits. |