stm32 /stm32h5 /STM32H503 /PWR /PWR_WUSCR

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Interpret as PWR_WUSCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CWUF1 0 (B_0x0)CWUF2 0 (B_0x0)CWUF3 0 (B_0x0)CWUF4 0 (B_0x0)CWUF5

CWUF2=B_0x0, CWUF3=B_0x0, CWUF5=B_0x0, CWUF4=B_0x0, CWUF1=B_0x0

Description

PWR wakeup status clear register

Fields

CWUF1

clear wakeup pin flag for WUFx These bits are always read as 0.

0 (B_0x0): no effect

1 (B_0x1): writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware).

CWUF2

clear wakeup pin flag for WUFx These bits are always read as 0.

0 (B_0x0): no effect

1 (B_0x1): writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware).

CWUF3

clear wakeup pin flag for WUFx These bits are always read as 0.

0 (B_0x0): no effect

1 (B_0x1): writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware).

CWUF4

clear wakeup pin flag for WUFx These bits are always read as 0.

0 (B_0x0): no effect

1 (B_0x1): writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware).

CWUF5

clear wakeup pin flag for WUFx These bits are always read as 0.

0 (B_0x0): no effect

1 (B_0x1): writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware).

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