ECCE=B_0x0, SRAMER=B_0x0, ALE=B_0x0
RAMCFG memory 2 control register
| ECCE | ECC enable. This bit reset value is defined by the user option bit configuration. When set, it can be cleared by software only after writing the unlock sequence in the RAMCFG_MxECCKEYR register. Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 0 (B_0x0): ECC disabled 1 (B_0x1): ECC enabled |
| ALE | Address latch enable Note: This bit is reserved and must be kept at reset value in SRAM1 control register. 0 (B_0x0): Failing address not stored in the SRAMx ECC single/double error address registers 1 (B_0x1): Failing address stored in the SRAMx ECC single/double error address registers |
| SRAMER | SRAM erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_MxERKEYR register. Setting this bit starts the SRAM erase. This bit is automatically cleared by hardware at the end of the erase operation. 0 (B_0x0): No erase operation on going 1 (B_0x1): Erase operation on going |