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stm32 /stm32h5 /STM32H503 /RAMCFG /RAMCFG_M3ICR

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Interpret as RAMCFG_M3ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSEDC)CSEDC 0 (CDED)CDED

Description

RAMCFG memory 3 interrupt clear register 3

Fields

CSEDC

Clear ECC single error detected and corrected Writing 1 to this flag clears the SEDC bit in the RAMCFG_MxISR register. Reading this flag returns the SEDC value.
CDED

Clear ECC double error detected Writing 1 to this flag clears the DED bit in the RAMCFG_MxISR register. Reading this flag returns the DED value.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32