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stm32 /stm32h5 /STM32H503 /RCC /RCC_AHB1RSTR

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Interpret as RCC_AHB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPDMA1RST 0 (B_0x0)GPDMA2RST 0 (B_0x0)CRCRST 0 (B_0x0)RAMCFGRST

RAMCFGRST=B_0x0, GPDMA2RST=B_0x0, CRCRST=B_0x0, GPDMA1RST=B_0x0

Description

RCC AHB1 reset register

Fields

GPDMA1RST

GPDMA1 block reset Set and reset by software.

0 (B_0x0): does not reset GPDMA1 block (default after reset)

1 (B_0x1): resets GPDMA1 block
GPDMA2RST

GPDMA2 block reset Set and reset by software.

0 (B_0x0): does not reset GPDMA2 block (default after reset)

1 (B_0x1): resets GPDMA2 block
CRCRST

CRC block reset Set and reset by software.

0 (B_0x0): does not reset CRC block (default after reset)

1 (B_0x1): resets CRC block
RAMCFGRST

RAMCFG block reset Set and reset by software.

0 (B_0x0): does not reset RAMCFG block (default after reset)

1 (B_0x1): resets RAMCFG block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32