stm32 /stm32h5 /STM32H503 /RCC /RCC_AHB2ENR

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Interpret as RCC_AHB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOAEN 0 (B_0x0)GPIOBEN 0 (B_0x0)GPIOCEN 0 (B_0x0)GPIODEN 0 (B_0x0)GPIOHEN 0 (B_0x0)ADC1EN 0 (B_0x0)DAC12EN 0 (B_0x0)HASHEN 0 (B_0x0)RNGEN 0 (B_0x0)SRAM2EN

GPIOCEN=B_0x0, GPIOAEN=B_0x0, GPIOBEN=B_0x0, DAC12EN=B_0x0, SRAM2EN=B_0x0, GPIOHEN=B_0x0, GPIODEN=B_0x0, RNGEN=B_0x0, ADC1EN=B_0x0, HASHEN=B_0x0

Description

RCC AHB2 peripheral clock register

Fields

GPIOAEN

GPIOA clock enable Set and reset by software.

0 (B_0x0): GPIOA peripheral clock disabled (default after reset)

1 (B_0x1): GPIOA peripheral clock enabled

GPIOBEN

GPIOB clock enable Set and reset by software.

0 (B_0x0): GPIOB peripheral clock disabled (default after reset)

1 (B_0x1): GPIOB peripheral clock enabled

GPIOCEN

GPIOC clock enable Set and reset by software.

0 (B_0x0): GPIOC peripheral clock disabled (default after reset)

1 (B_0x1): GPIOC peripheral clock enabled

GPIODEN

GPIOD clock enable Set and reset by software.

0 (B_0x0): GPIOD peripheral clock disabled (default after reset)

1 (B_0x1): GPIOD peripheral clock enabled

GPIOHEN

GPIOH clock enable Set and reset by software.

0 (B_0x0): GPIOH peripheral clock disabled (default after reset)

1 (B_0x1): GPIOH peripheral clock enabled

ADC1EN

ADC1 peripherals clock enabled Set and reset by software.

0 (B_0x0): ADC1 peripherals clock disabled (default after reset)

1 (B_0x1): ADC1 peripherals clock enabled

DAC12EN

DAC clock enable Set and reset by software.

0 (B_0x0): DAC peripheral clock disabled (default after reset)

1 (B_0x1): DAC peripheral clock enabled

HASHEN

HASH clock enable Set and reset by software.

0 (B_0x0): HASH peripheral clock disabled (default after reset)

1 (B_0x1): HASH peripheral clock enabled

RNGEN

RNG clock enable Set and reset by software.

0 (B_0x0): RNG peripheral clock disabled (default after reset)

1 (B_0x1): RNG peripheral clock enabled

SRAM2EN

SRAM2 clock enable Set and reset by software.

0 (B_0x0): SRAM2 clock disabled

1 (B_0x1): SRAM2 clock enabled (default after reset)

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