stm32 /stm32h5 /STM32H503 /RCC /RCC_AHB2LPENR

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Interpret as RCC_AHB2LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOALPEN 0 (B_0x0)GPIOBLPEN 0 (B_0x0)GPIOCLPEN 0 (B_0x0)GPIODLPEN 0 (B_0x0)GPIOHLPEN 0 (B_0x0)ADC1LPEN 0 (B_0x0)DAC12LPEN 0 (B_0x0)HASHLPEN 0 (B_0x0)RNGLPEN 0 (B_0x0)SRAM2LPEN

GPIOHLPEN=B_0x0, GPIOCLPEN=B_0x0, RNGLPEN=B_0x0, GPIOBLPEN=B_0x0, GPIOALPEN=B_0x0, HASHLPEN=B_0x0, DAC12LPEN=B_0x0, SRAM2LPEN=B_0x0, GPIODLPEN=B_0x0, ADC1LPEN=B_0x0

Description

RCC AHB2 sleep clock register

Fields

GPIOALPEN

GPIOA clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOA peripheral clock disabled during sleep mode

1 (B_0x1): GPIOA peripheral clock enabled during sleep mode (default after reset)

GPIOBLPEN

GPIOB clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOB peripheral clock disabled during sleep mode

1 (B_0x1): GPIOB peripheral clock enabled during sleep mode (default after reset)

GPIOCLPEN

GPIOC clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOC peripheral clock disabled during sleep mode

1 (B_0x1): GPIOC peripheral clock enabled during sleep mode (default after reset)

GPIODLPEN

GPIOD clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOD peripheral clock disabled during sleep mode

1 (B_0x1): GPIOD peripheral clock enabled during sleep mode (default after reset)

GPIOHLPEN

GPIOH clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOH peripheral clock disabled during sleep mode

1 (B_0x1): GPIOH peripheral clock enabled during sleep mode (default after reset)

ADC1LPEN

ADC1 peripherals clock enable during sleep mode Set and reset by software.

0 (B_0x0): ADC1 peripherals clock disabled during sleep mode

1 (B_0x1): ADC1 peripherals clock enabled during sleep mode (default after reset)

DAC12LPEN

DAC clock enable during sleep mode Set and reset by software.

0 (B_0x0): DAC peripheral clock disabled during sleep mode

1 (B_0x1): DAC peripheral clock enabled during sleep mode (default after reset)

HASHLPEN

HASH clock enable during sleep mode Set and reset by software.

0 (B_0x0): HASH peripheral clock disabled during sleep mode

1 (B_0x1): HASH peripheral clock enabled during sleep mode (default after reset)

RNGLPEN

RNG clock enable during sleep mode Set and reset by software.

0 (B_0x0): RNG peripheral clock disabled during sleep mode

1 (B_0x1): RNG peripheral clock enabled during sleep mode (default after reset)

SRAM2LPEN

SRAM2 clock enable during sleep mode Set and reset by software.

0 (B_0x0): SRAM2 peripheral clock disabled during sleep mode

1 (B_0x1): SRAM2 peripheral clock enabled during sleep mode (default after reset)

Links

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