FDCAN1EN=B_0x0, LPTIM2EN=B_0x0, DTSEN=B_0x0
RCC APB1 peripheral clock register
| DTSEN | DTS clock enable Set and reset by software. 0 (B_0x0): DTS peripheral clock disabled (default after reset) 1 (B_0x1): DTS peripheral clock enabled |
| LPTIM2EN | LPTIM2 clock enable Set and reset by software. 0 (B_0x0): LPTIM2 peripheral clock disabled (default after reset) 1 (B_0x1): LPTIM2 peripheral clock enabled |
| FDCAN1EN | FDCAN1 peripheral clock enable Set and reset by software. 0 (B_0x0): FDCAN1 peripheral clock disabled (default after reset) 1 (B_0x1): FDCAN1 peripheral clock enabled |