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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB1HLPENR

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Interpret as RCC_APB1HLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DTSLPEN 0 (B_0x0)LPTIM2LPEN 0 (B_0x0)FDCAN1LPEN

FDCAN1LPEN=B_0x0, DTSLPEN=B_0x0, LPTIM2LPEN=B_0x0

Description

RCC APB1 sleep clock register

Fields

DTSLPEN

DTS clock enable during sleep mode Set and reset by software.

0 (B_0x0): DTS peripheral clock disabled during sleep mode

1 (B_0x1): DTS peripheral clock enabled during sleep mode (default after reset)
LPTIM2LPEN

LPTIM2 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM2 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM2 peripheral clock enabled during sleep mode (default after reset)
FDCAN1LPEN

FDCAN1 peripheral clock enable during sleep mode Set and reset by software.

0 (B_0x0): FDCAN1 peripheral clock disabled during sleep mode

1 (B_0x1): FDCAN1 peripheral clock enabled during sleep mode (default after reset)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32