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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB1HRSTR

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Interpret as RCC_APB1HRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DTSRST 0 (B_0x0)LPTIM2RST 0 (B_0x0)FDCAN1RST

LPTIM2RST=B_0x0, DTSRST=B_0x0, FDCAN1RST=B_0x0

Description

RCC APB1 peripheral high reset register

Fields

DTSRST

DTS block reset Set and reset by software.

0 (B_0x0): does not reset the DTS block (default after reset)

1 (B_0x1): resets the DTS block
LPTIM2RST

LPTIM2 block reset Set and reset by software.

0 (B_0x0): does not reset the LPTIM2 block (default after reset)

1 (B_0x1): resets the LPTIM2 block
FDCAN1RST

FDCAN1 block reset Set and reset by software.

0 (B_0x0): does not reset the FDCAN1 block (default after reset)

1 (B_0x1): resets the FDCAN1 block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32