TIM3EN=B_0x0, I2C1EN=B_0x0, USART3EN=B_0x0, SPI2EN=B_0x0, OPAMPEN=B_0x0, TIM7EN=B_0x0, USART2EN=B_0x0, I2C2EN=B_0x0, CRSEN=B_0x0, TIM2EN=B_0x0, COMPEN=B_0x0, SPI3EN=B_0x0, WWDGEN=B_0x0, TIM6EN=B_0x0, I3C1EN=B_0x0
RCC APB1 peripheral clock register
| TIM2EN | TIM2 clock enable Set and reset by software. 0 (B_0x0): TIM2 peripheral clock disabled (default after reset) 1 (B_0x1): TIM2 peripheral clock enabled |
| TIM3EN | TIM3 clock enable Set and reset by software. 0 (B_0x0): TIM3 peripheral clock disabled (default after reset) 1 (B_0x1): TIM3 peripheral clock enabled |
| TIM6EN | TIM6 clock enable Set and reset by software. 0 (B_0x0): TIM6 peripheral clock disabled (default after reset) 1 (B_0x1): TIM6 peripheral clock enabled |
| TIM7EN | TIM7 clock enable Set and reset by software. 0 (B_0x0): TIM7 peripheral clock disabled (default after reset) 1 (B_0x1): TIM7 peripheral clock enabled |
| WWDGEN | WWDG clock enable Set and reset by software. 0 (B_0x0): WWDG peripheral clock disabled (default after reset) 1 (B_0x1): WWDG peripheral clock enabled |
| OPAMPEN | OPAMP clock enable Set and reset by software. 0 (B_0x0): OPAMP peripheral clock disabled (default after reset) 1 (B_0x1): OPAMP peripheral clock enabled |
| SPI2EN | SPI2 clock enable Set and reset by software. 0 (B_0x0): SPI2 peripheral clock disabled (default after reset) 1 (B_0x1): SPI2 peripheral clock enabled |
| SPI3EN | SPI3 clock enable Set and reset by software. 0 (B_0x0): SPI3 peripheral clock disabled (default after reset) 1 (B_0x1): SPI3 peripheral clock enabled |
| COMPEN | COMP clock enable Set and reset by software. 0 (B_0x0): COMP peripheral clock disabled (default after reset) 1 (B_0x1): COMP peripheral clock enabled |
| USART2EN | USART2 clock enable Set and reset by software. 0 (B_0x0): USART2 peripheral clock disabled (default after reset) 1 (B_0x1): USART2 peripheral clock enabled |
| USART3EN | USART3 clock enable Set and reset by software. 0 (B_0x0): USART3 peripheral clock disabled (default after reset) 1 (B_0x1): USART3 peripheral clock enabled |
| I2C1EN | I2C1 clock enable Set and reset by software. 0 (B_0x0): I2C1 peripheral clock disabled (default after reset) 1 (B_0x1): I2C1 peripheral clock enabled |
| I2C2EN | I2C2 clock enable Set and reset by software. 0 (B_0x0): I2C2 peripheral clock disabled (default after reset) 1 (B_0x1): I2C2 peripheral clock enabled |
| I3C1EN | I3C1 clock enable Set and reset by software. 0 (B_0x0): I3C1 peripheral clock disabled (default after reset) 1 (B_0x1): I3C1 peripheral clock enabled |
| CRSEN | CRS clock enable Set and reset by software. 0 (B_0x0): CRS peripheral clock disabled (default after reset) 1 (B_0x1): CRS peripheral clock enabled |