I2C2LPEN=B_0x0, SPI2LPEN=B_0x0, I2C1LPEN=B_0x0, COMPLPEN=B_0x0, USART3LPEN=B_0x0, WWDGLPEN=B_0x0, TIM3LPEN=B_0x0, OPAMPLPEN=B_0x0, TIM7LPEN=B_0x0, CRSLPEN=B_0x0, SPI3LPEN=B_0x0, I3C1LPEN=B_0x0, TIM2LPEN=B_0x0, USART2LPEN=B_0x0, TIM6LPEN=B_0x0
RCC APB1 sleep clock register
| TIM2LPEN | TIM2 clock enable during sleep mode Set and reset by software. 0 (B_0x0): TIM2 peripheral clock disabled during sleep mode 1 (B_0x1): TIM2 peripheral clock enabled during sleep mode (default after reset) |
| TIM3LPEN | TIM3 clock enable during sleep mode Set and reset by software. 0 (B_0x0): TIM3 peripheral clock disabled during sleep mode 1 (B_0x1): TIM3 peripheral clock enabled during sleep mode (default after reset) |
| TIM6LPEN | TIM6 clock enable during sleep mode Set and reset by software. 0 (B_0x0): TIM6 peripheral clock disabled during sleep mode 1 (B_0x1): TIM6 peripheral clock enabled during sleep mode (default after reset) |
| TIM7LPEN | TIM7 clock enable during sleep mode Set and reset by software. 0 (B_0x0): TIM7 peripheral clock disabled during sleep mode 1 (B_0x1): TIM7 peripheral clock enabled during sleep mode (default after reset) |
| WWDGLPEN | WWDG clock enable during sleep mode Set and reset by software. 0 (B_0x0): WWDG peripheral clock disabled during sleep mode 1 (B_0x1): WWDG peripheral clock enabled during sleep mode (default after reset) |
| OPAMPLPEN | OPAMP clock enable during sleep mode Set and reset by software. 0 (B_0x0): OPAMP peripheral clock disabled during sleep mode 1 (B_0x1): OPAMP peripheral clock enabled during sleep mode (default after reset) |
| SPI2LPEN | SPI2 clock enable during sleep mode Set and reset by software. 0 (B_0x0): SPI2 peripheral clock disabled during sleep mode 1 (B_0x1): SPI2 peripheral clock enabled during sleep mode (default after reset) |
| SPI3LPEN | SPI3 clock enable during sleep mode Set and reset by software. 0 (B_0x0): SPI3 peripheral clock disabled during sleep mode 1 (B_0x1): SPI3 peripheral clock enabled during sleep mode (default after reset) |
| COMPLPEN | COMP clock enable during sleep mode Set and reset by software. 0 (B_0x0): COMP peripheral clock disabled during sleep mode 1 (B_0x1): COMP peripheral clock enabled during sleep mode (default after reset) |
| USART2LPEN | USART2 clock enable during sleep mode Set and reset by software. 0 (B_0x0): USART2 peripheral clock disabled during sleep mode 1 (B_0x1): USART2 peripheral clock enabled during sleep mode (default after reset) |
| USART3LPEN | USART3 clock enable during sleep mode Set and reset by software. 0 (B_0x0): USART3 peripheral clock disabled during sleep mode 1 (B_0x1): USART3 peripheral clock enabled during sleep mode (default after reset) |
| I2C1LPEN | I2C1 clock enable during sleep mode Set and reset by software. 0 (B_0x0): I2C1 peripheral clock disabled during sleep mode 1 (B_0x1): I2C1 peripheral clock enabled during sleep mode (default after reset) |
| I2C2LPEN | I2C2 clock enable during sleep mode Set and reset by software. 0 (B_0x0): I2C2 peripheral clock disabled during sleep mode 1 (B_0x1): I2C2 peripheral clock enabled during sleep mode (default after reset) |
| I3C1LPEN | I3C1 clock enable during sleep mode Set and reset by software. 0 (B_0x0): I3C1 peripheral clock disabled during sleep mode 1 (B_0x1): I3C1 peripheral clock enabled during sleep mode (default after reset) |
| CRSLPEN | CRS clock enable during sleep mode Set and reset by software. 0 (B_0x0): CRS peripheral clock disabled during sleep mode 1 (B_0x1): CRS peripheral clock enabled during sleep mode (default after reset) |