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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB1LRSTR

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Interpret as RCC_APB1LRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2RST 0 (B_0x0)TIM3RST 0 (B_0x0)TIM6RST 0 (B_0x0)TIM7RST 0 (B_0x0)OPAMPRST 0 (B_0x0)SPI2RST 0 (B_0x0)SPI3RST 0 (B_0x0)COMPRST 0 (B_0x0)USART2RST 0 (B_0x0)USART3RST 0 (B_0x0)I2C1RST 0 (B_0x0)I2C2RST 0 (B_0x0)I3C1RST 0 (B_0x0)CRSRST

TIM6RST=B_0x0, USART3RST=B_0x0, TIM3RST=B_0x0, CRSRST=B_0x0, SPI3RST=B_0x0, USART2RST=B_0x0, I3C1RST=B_0x0, COMPRST=B_0x0, I2C2RST=B_0x0, I2C1RST=B_0x0, OPAMPRST=B_0x0, TIM7RST=B_0x0, TIM2RST=B_0x0, SPI2RST=B_0x0

Description

RCC APB1 peripheral low reset register

Fields

TIM2RST

TIM2 block reset Set and reset by software.

0 (B_0x0): does not reset the TIM2 block (default after reset)

1 (B_0x1): resets the TIM2 block
TIM3RST

TIM3 block reset Set and reset by software.

0 (B_0x0): does not reset the TIM3 block (default after reset)

1 (B_0x1): resets the TIM3 block
TIM6RST

TIM6 block reset Set and reset by software.

0 (B_0x0): does not reset the TIM6 block (default after reset)

1 (B_0x1): resets the TIM6 block
TIM7RST

TIM7 block reset Set and reset by software.

0 (B_0x0): does not reset the TIM7 block (default after reset)

1 (B_0x1): resets the TIM7 block
OPAMPRST

OPAMP block reset Set and reset by software.

0 (B_0x0): does not reset the OPAMP block (default after reset)

1 (B_0x1): resets the OPAMP block
SPI2RST

SPI2 block reset Set and reset by software.

0 (B_0x0): does not reset the SPI2 block (default after reset)

1 (B_0x1): resets the SPI2 block
SPI3RST

SPI3 block reset Set and reset by software.

0 (B_0x0): does not reset the SPI3 block (default after reset)

1 (B_0x1): resets the SPI3 block
COMPRST

COMP block reset Set and reset by software.

0 (B_0x0): does not reset the COMP block (default after reset)

1 (B_0x1): resets the COMP block
USART2RST

USART2 block reset Set and reset by software.

0 (B_0x0): does not reset the USART2 block (default after reset)

1 (B_0x1): resets the USART2 block
USART3RST

USART3 block reset Set and reset by software.

0 (B_0x0): does not reset the USART3 block (default after reset)

1 (B_0x1): resets the USART3 block
I2C1RST

I2C1 block reset Set and reset by software.

0 (B_0x0): does not reset the I2C1 block (default after reset)

1 (B_0x1): resets the I2C1 block
I2C2RST

I2C2 block reset Set and reset by software.

0 (B_0x0): does not reset the I2C2 block (default after reset)

1 (B_0x1): resets the I2C2 block
I3C1RST

I3C1 block reset Set and reset by software.

0 (B_0x0): does not reset the I3C1 block (default after reset)

1 (B_0x1): resets the I3C1 block
CRSRST

CRS block reset Set and reset by software.

0 (B_0x0): does not reset the CRS block (default after reset)

1 (B_0x1): resets the CRS block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32