stm32 /stm32h5 /STM32H503 /RCC /RCC_APB2ENR

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Interpret as RCC_APB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1EN 0 (B_0x0)SPI1EN 0 (B_0x0)USART1EN 0 (B_0x0)USBFSEN

USART1EN=B_0x0, SPI1EN=B_0x0, USBFSEN=B_0x0, TIM1EN=B_0x0

Description

RCC APB2 peripheral clock register

Fields

TIM1EN

TIM1 clock enable Set and reset by software.

0 (B_0x0): TIM1 peripheral clock disabled (default after reset)

1 (B_0x1): TIM1 peripheral clock enabled

SPI1EN

SPI1 clock enable Set and reset by software.

0 (B_0x0): SPI1 peripheral clock disabled (default after reset)

1 (B_0x1): SPI1 peripheral clock enabled

USART1EN

USART1 clock enable Set and reset by software.

0 (B_0x0): USART1 peripheral clock disabled (default after reset)

1 (B_0x1): USART1 peripheral clock enabled

USBFSEN

USBFS clock enable Set and reset by software.

0 (B_0x0): USBFS peripheral clock disabled (default after reset)

1 (B_0x1): USBFS peripheral clock enabled

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