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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB2LPENR

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Interpret as RCC_APB2LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1LPEN 0 (B_0x0)SPI1LPEN 0 (B_0x0)USART1LPEN 0 (B_0x0)USBFSLPEN

USART1LPEN=B_0x0, SPI1LPEN=B_0x0, TIM1LPEN=B_0x0, USBFSLPEN=B_0x0

Description

RCC APB2 sleep clock register

Fields

TIM1LPEN

TIM1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): TIM1 peripheral clock disabled during sleep mode

1 (B_0x1): TIM1 peripheral clock enabled during sleep mode (default after reset)
SPI1LPEN

SPI1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): SPI1 peripheral clock disabled during sleep mode

1 (B_0x1): SPI1 peripheral clock enabled during sleep mode (default after reset)
USART1LPEN

USART1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): USART1 peripheral clock disabled during sleep mode

1 (B_0x1): USART1 peripheral clock enabled during sleep mode (default after reset)
USBFSLPEN

USBFS clock enable during sleep mode Set and reset by software.

0 (B_0x0): USBFS peripheral clock disabled during sleep mode

1 (B_0x1): USBFS peripheral clock enabled during sleep mode (default after reset)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32