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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB2RSTR

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Interpret as RCC_APB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1RST 0 (B_0x0)SPI1RST 0 (B_0x0)USART1RST 0 (B_0x0)USBFSRST

TIM1RST=B_0x0, USART1RST=B_0x0, USBFSRST=B_0x0, SPI1RST=B_0x0

Description

RCC APB2 peripheral reset register

Fields

TIM1RST

TIM1 block reset Set and reset by software.

0 (B_0x0): does not reset the TIM1 block (default after reset)

1 (B_0x1): resets the TIM1 block
SPI1RST

SPI1 block reset Set and reset by software.

0 (B_0x0): does not reset the SPI1 block (default after reset)

1 (B_0x1): resets the SPI1 block
USART1RST

USART1 block reset Set and reset by software.

0 (B_0x0): does not reset the USART1 block (default after reset)

1 (B_0x1): resets the USART1 block
USBFSRST

USBFS block reset Set and reset by software.

0 (B_0x0): does not reset the USBFS block (default after reset)

1 (B_0x1): resets the USBFS block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32