stm32 /stm32h5 /STM32H503 /RCC /RCC_APB3LPENR

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Interpret as RCC_APB3LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SBSLPEN 0 (B_0x0)LPUART1LPEN 0 (B_0x0)I3C2LPEN 0 (B_0x0)LPTIM1LPEN 0 (B_0x0)VREFLPEN 0 (B_0x0)RTCAPBLPEN

I3C2LPEN=B_0x0, LPTIM1LPEN=B_0x0, RTCAPBLPEN=B_0x0, VREFLPEN=B_0x0, LPUART1LPEN=B_0x0, SBSLPEN=B_0x0

Description

RCC APB3 sleep clock register

Fields

SBSLPEN

SBS clock enable during sleep mode Set and reset by software.

0 (B_0x0): SBS peripheral clock disabled during sleep mode

1 (B_0x1): SBS peripheral clock enabled during sleep mode (default after reset)

LPUART1LPEN

LPUART1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPUART1 peripheral clock disabled during sleep mode

1 (B_0x1): LPUART1 peripheral clock enabled during sleep mode (default after reset)

I3C2LPEN

I3C2 clock enable during sleep mode Set and reset by software.

0 (B_0x0): I3C2 peripheral clock disabled during sleep mode

1 (B_0x1): I3C2 peripheral clock enabled during sleep mode (default after reset)

LPTIM1LPEN

LPTIM1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM1 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM1 peripheral clock enabled during sleep mode (default after reset)

VREFLPEN

VREF clock enable during sleep mode Set and reset by software.

0 (B_0x0): VREF peripheral clock disabled during sleep mode

1 (B_0x1): VREF peripheral clock enabled during sleep mode (default after reset)

RTCAPBLPEN

RTC APB interface clock enable during sleep mode Set and reset by software.

0 (B_0x0): RTC APB interface clock disabled during sleep mode

1 (B_0x1): RTC APB interface clock enabled during sleep mode (default after reset)

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